View HT48R30A_150847.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HT48R30A-1 8-Bit Microcontroller
Features
* * * * * * * * *
Operating voltage: fSYS=4MHz: 3.3V~5.5V fSYS=8MHz: 4.5V~5.5V Low voltage reset function 25 bidirectional I/O lines (max.) 1 interrupt input shared with an I/O line 8-bit programmable timer/event counter with overflow interrupt and 8-stage prescaler On-chip RC oscillator, external crystal and RC oscillator 32768Hz crystal oscillator for timing purposes only Watchdog Timer 204814 program memory ROM
* * * * * * * * * *
968 data memory RAM Buzzer driving pair and PFD supported HALT function and wake-up feature reduce power consumption 4-level subroutine nesting Up to 0.5ms instruction cycle with 8MHz system clock at VDD=5V Bit manipulation instruction 14-bit table read instruction 63 powerful instructions All instructions in one or two machine cycles 24/28-pin SKDIP/SOP package
General Description
The device is an 8-bit high performance RISC-like microcontroller designed for multiple I/O product applications. The device is particularly suitable for use in products such as remote controllers, fan/light controllers, washing machine controllers, scales, toys and various subsystem controllers. A HALT feature is included to reduce power consumption.
Rev. 1.10
1
July 2, 2001
HT48R30A-1
Block Diagram
IN T /P G 0
In te rru p t C ir c u it STACK 4 L e v e ls TM R0 IN T C TM R0C PG0 In s tr u c tio n R e g is te r M U X W DTS DATA M e m o ry W D T P r e s c a le r WDT M U X M U X P r e s c a le r T M R /P C 0 M
U X
fS
YS
P ro g ra m ROM
P ro g ra m C o u n te r
E N /D IS
S Y S C L K /4 RTC W DT OSC OSC
MP
PAC In s tr u c tio n D ecoder ALU T im in g G e n e ra to r S h ifte r MUX PA
PORT A
PA0~PA7
STATUS PG1 PG2
B Z /B Z PBC PB PCC PORT C PORT B PB0~PB7
O SC 2/ PG2
OS P R V V
C 1/ G1 ES DD SS
ACC In te rn a l RC OSC O p tio n R O M O T P o n ly
PC
PC0~PC5
PGC PG
PORT G
PG 0~PG 2
Rev. 1.10
2
July 2, 2001
HT48R30A-1
Pin Assignment
PB5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PB4 PB5 1 2 3 4 5 6 7 8 9 10 11 12 PB4 PA3 PA2 PA1 PA0 PB3 PB2 P B 1 /B Z P B 0 /B Z VSS P G 0 /IN T 24 23 22 21 20 19 18 17 16 15 14 13 PB6 PB7 PA4 PA5 PA6 PA7 O S C 2 /P G 2 O S C 1 /P G 1 VDD RES PC2 P C 0 /T M R PA3 PA2 PA1 PA0 PB3 PB2 P B 1 /B Z P B 0 /B Z VSS P G 0 /IN T P C 0 /T M R PC1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PB6 PB7 PA4 PA5 PA6 PA7 O S C 2 /P G 2 O S C 1 /P G 1 VDD RES PC5 PC4 PC3 PC2
H T 4 8 R 3 0 A -1 2 4 S K D IP -A /S O P -A
H T 4 8 R 3 0 A -1 2 8 S K D IP -A /S O P -A
Pin Description
Pin Name I/O ROM Code Option Description
PA0~PA7
Bidirectional 8-bit input/output port. Each bit can be configPull-high* ured as a wake-up input by ROM code option. Software instrucWake-up tions determine the CMOS output or Schmitt trigger or CMOS I/O CMOS/Schmitt input (depends on an options) with pull-high resistor (determined trigger Input by 1-bit pull-high options). Bidirectional 8-bit input/output port. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by pull-high options). The PB0 and PB1 are pin-shared with the BZ and BZ, respectively. Once the PB0 or PB1 is selected as buzzer driving outputs, the output signals come from an internal PFD generator (shared with timer/event counter). Negative power supply, ground Bidirectional I/O lines. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by 1-bit pull-high options). This external interrupt input is pin-shared with PG0. The external interrupt input is activated on a high to low transition. Bidirectional I/O lines. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by 1-bit pull-high options). The timer input are pin-shared with PC0.
PB0/BZ PB1/BZ PB2~PB7
I/O
Pull-high* PB0 or BZ PB1 or BZ
VSS
3/4
3/4
PG0/INT
I/O
Pull-high*
PC0/TMR PC1~PC5
I/O
Pull-high*
Rev. 1.10
3
July 2, 2001
HT48R30A-1
Pin Name I/O RES VDD I 3/4 ROM Code Option 3/4 3/4 Positive power supply Description Schmitt trigger reset input. Active low
OSC1/PG1 OSC2/PG2
I O
OSC1, OSC2 are connected to an RC network or Crystal (determined by ROM code option) for the internal system clock. In the Pull-high* case of RC operation, OSC2 is the output terminal for 1/4 system clock. These two pins can also be optioned as an RTC oscilCrystal lator (32768Hz) or I/O lines. In these two cases, the system or RC or Int. RC+I/O clock comes from an internal RC oscillator whose frequency has 4 options (3.2MHz, 1.6MHz, 800kHz, 400kHz). If the I/O option or Int. is selected, the pull-high options can also be enabled or disRC+RTC abled. Otherwise the PG1 and PG2 are used as internal registers (pull-high resistors are always disabled).
Note: * The pull-high resistors of each I/O port (PA, PB, PC, PG) are controlled by 1-bit ROM code option. CMOS or Schmitt trigger option of port A is controlled by 1-bit ROM code option.
Absolute Maximum Ratings
Supply Voltage ...............VSS-0.3V to VSS+5.5V Input Voltage.................VSS-0.3V to VDD+0.3V Storage Temperature ................-50C to 125C Operating Temperature ..............-40C to 85C
Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol VDD1 VDD2 IDD1 IDD2 IDD3 ISTB1 Parameter Operating Voltage Operating Voltage Operating Current (Crystal OSC) Operating Current (RC OSC) Operating Current (Crystal OSC) Test Conditions VDD 3/4 3/4 3.3V 5V 3.3V 5V 5V Conditions fSYS=4MHz fSYS=8MHz No load, fSYS=4MHz No load, fSYS=4MHz No load, fSYS=8MHz Min. 3.3 4.5 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Typ. 3/4 3/4 1 3 1 3 4 3/4 3/4
Ta=25C Max. 5.5 5.5 2 5 2 5 8 5 10 Unit V V mA mA mA mA mA mA mA
3.3V Standby Current No load, system HALT (WDT Enabled RTC Off) 5V
Rev. 1.10
4
July 2, 2001
HT48R30A-1
Symbol ISTB2 ISTB3 VIL1 VIH1 VIL2 VIH2 IOL IOH RPH VLVR Parameter Test Conditions VDD Conditions Min. 3/4 3/4 3/4 3/4 0 0.7VDD 0 0.9VDD 4 10 -2 -5 40 10 2.7 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 8 20 -4 -10 60 30 3.0 Max. 1 2 5 10 0.3VDD VDD 0.4VDD VDD 3/4 3/4 3/4 3/4 80 50 3.3 Unit mA mA mA mA V V V V mA mA mA mA kW kW V Ta=25C Test Conditions VDD 3.3V 5V 3.3V 5V 3.3V 5V 3.3V 5V 3.3V 5V Conditions 3/4 3/4 3/4 3/4 3.2MHz option 3/4 3/4 3/4 3/4 Min. Typ. Max. Unit 400 400 400 400 3/4 3/4 3/4 3/4 4000 8000 4000 8000 kHz kHz kHz kHz kHz kHz kHz kHz ms ms ms ms
3.3V Standby Current No load, system HALT (WDT Disabled RTC Off) 5V 3.3V Standby Current No load, system HALT (WDT Disabled, RTC On) 5V Input Low Voltage for I/O Ports Input High Voltage for I/O Ports Input Low Voltage (RES) Input High Voltage (RES) I/O Port Sink Current I/O Port Source Current Pull-high Resistance Low Voltage Reset 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
3.3V VOL=0.1VDD 5V 5V 3.3V 5V 3/4 VOL=0.1VDD VOH=0.9VDD 3/4 3/4 3.3V option 3.3V VOH=0.9VDD
A.C. Characteristics
Symbol fSYS1 fSYS2 fSYS3 fTIMER tWDTOSC tWDT1 Parameter System Clock (Crystal OSC) System Clock (RC OSC) System Clock (Internal RC) Timer I/P Frequency (TMR0/TMR1) Watchdog Oscillator Watchdog Time-out Period (WDT OSC)
1600 2500 3500 2000 3200 4500 0 0 43 36 11 9 3/4 3/4 86 72 22 18 4000 8000 168 144 43 37
3.3V Without WDT 5V prescaler
Rev. 1.10
5
July 2, 2001
HT48R30A-1
Symbol tWDT2 tWDT3 tRES tSST tINT Parameter Watchdog Time-out Period (System Clock) Watchdog Time-out Period (RTC OSC) External Reset Low Pulse Width System Start-up Timer Period Interrupt Pulse Width Test Conditions VDD 3/4 3/4 3/4 3/4 3/4 Conditions Without WDT prescaler Without WDT prescaler 3/4 Wake-up from HALT 3/4 Min. Typ. Max. Unit 3/4 3/4 1 3/4 1 1024 7.812 3/4 1024 3/4 3/4 3/4 3/4 3/4 3/4 tSYS ms ms tSYS ms
Functional Description
Execution flow The system clock for the microcontroller is derived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program counter - PC The program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed and its contents
S y s te m O S C 2 (R C C lo c k o n ly ) PC PC PC+1 PC+2 T1 T2 T3 T4 T1 T2
specify a full range of program memory. After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call or return from subroutine, initial reset, internal interrupt, external interrupt or return from interrupt, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction.
T3 T4 T1 T2 T3 T4
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution flow
Rev. 1.10 6 July 2, 2001
HT48R30A-1
The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within the current program ROM page. When a control transfer takes place, an additional dummy cycle is required. Program memory - ROM The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 204814 bits, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage:
* Location 000H
n00H nFFH 000H 004H 008H D e v ic e In itia liz a tio n P r o g r a m E x te r n a l In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e
P ro g ra m M e m o ry L o o k - u p T a b le ( 2 5 6 w o r d s )
700H 7FFH
L o o k - u p T a b le ( 2 5 6 w o r d s ) 1 4 b its N o te : n ra n g e s fro m 0 to 7
This area is reserved for program initialization. After chip reset, the program always begins execution at location 000H.
* Location 004H
Program memory ter interrupt service program. If a timer interrupt results from a timer/event counter overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H .
* Table location
This area is reserved for the external interrupt service program. If the INT input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004H.
* Location 008H
This area is reserved for the timer/event counMode Initial Reset External Interrupt Timer/Event Counter Overflow Skip Loading PCL Jump, Call Branch Return from Subroutine *10 #10 S10 *9 #9 S9 *8 #8 S8
Any location in the program memory space can be used as look-up tables. The instructions "TABRDC [m]" (the current page, one page=256 words) and "TABRDL [m]" (the last Program Counter
*10 0 0 0
*9 0 0 0
*8 0 0 0
*7 0 0 0 @7 #7 S7
*6 0 0 0 @6 #6 S6
*5 0 0 0 PC+2 @5 #5 S5
*4 0 0 0 @4 #4 S4
*3 0 0 1 @3 #3 S3
*2 0 1 0 @2 #2 S2
*1 0 0 0 @1 #1 S1
*0 0 0 0 @0 #0 S0
Program counter Note: *10~*0: Program counter bits #10~#0: Instruction code bits
Rev. 1.10 7
S10~S0: Stack register bits @7~@0: PCL bits
July 2, 2001
HT48R30A-1
page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, and the remaining 2-bits words are read as "0". The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H), which indicates the table location. Before accessing the table, the location must be placed in the TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt is supposed to be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions require two cycles to complete the operation. These areas may function as normal program memory depending upon the requirements. Stack register - STACK This is a special part of the memory which is used to save the contents of the program counter (PC) only. The stack is organized into 4 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Instruction TABRDC [m] TABRDL [m] *10 P10 1 *9 P9 1 *8 P8 1 *7 @7 @7 stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the stack pointer is (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a "CALL" is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent 4 return addresses are stored). Data memory - RAM The data memory is designed with 1158 bits. The data memory is divided into two functional groups: special function registers and general purpose data memory (968). Most are read/write, but some are read only. The special function registers include the indirect addressing registers (R0;00H), timer/event counter (TMR;0DH), timer/event counter control register (TMRC;0EH), program counter lower-order byte register (PCL;06H), memory pointer registers (MP;01H), accumulator (ACC;05H), table pointer (TBLP;07H), table higher-order byte register (TBLH;08H), status register (STATUS;0AH), interrupt control register Table Location *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0
Table location Note: *10~*0: Table location bits @7~@0: Table pointer bits
Rev. 1.10 8 July 2, 2001
P10~P8: Current program counter bits
HT48R30A-1
(INTC;0BH), Watchdog Timer option setting register (WDTS;09H), I/O registers (PA;12H, PB;14H, PC;16H, PG;1EH) and I/O control registers (PAC;13H, PBC;15H, PCC;17H, PGC;1FH). The remaining space before the 20H is reserved for future expanded usage and reading these locations will get "00H". The
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H PG PGC G e n e ra l P u rp o s e DATA M EM ORY (9 6 B y te s ) :U nused R e a d a s "0 0 " PA PAC PB PBC PC PCC TM R TM RC ACC PCL TBLP TBLH W DTS STATUS IN T C S p e c ia l P u r p o s e DATA M EM ORY In d ir e c t A d d r e s s in g R e g is te r MP
general purpose data memory, addressed from 20H to 7FH, is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by "SET [m].i" and "CLR [m].i". They are also indirectly accessible through memory pointer registers (MP). Indirect addressing register Location 00H is indirect addressing register that is not physically implemented. Any read/write operation of [00H] will access data memory pointed to by MP. Reading location 00H itself indirectly will return the result 00H. Writing indirectly results in no operation. The memory pointer register (MP) is 8-bit registers. Accumulator The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator. Arithmetic and logic unit - ALU This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
* Arithmetic operations (ADD, ADC, SUB,
SBC, DAA)
* Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ ....)
7FH 80H FFH
The ALU not only saves the results of a data operation but also changes the status register.
RAM mapping
Rev. 1.10
9
July 2, 2001
HT48R30A-1
Status register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PD), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PD flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PD flag. In addition operations related to the status register may give different results from those intended. The TO flag can be affected only by system power-up, a WDT time-out or executing the "CLR WDT" or "HALT" instruction. The PD flag can be affected only by executing the "HALT" or "CLR WDT" instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status are Labels C Bits 0 important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. Interrupt The device provides an external interrupt and internal timer/event counter interrupts. The Interrupt Control Register (INTC;0BH) contains the interrupt control bits to set the enable/disable and the interrupt request flags. Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control Function C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PD is cleared by system power-up or executing the "CLR WDT" instruction. PD is set by executing the "HALT" instruction. TO is cleared by system power-up or executing the "CLR WDT" or "HALT" instruction. TO is set by a WDT time-out. Unused bit, read as "0" Unused bit, read as "0" Status register
Rev. 1.10 10 July 2, 2001
AC Z OV PD TO 3/4 3/4
1 2 3 4 5 6 7
HT48R30A-1
transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. External interrupts are triggered by a high to low transition of the INT and the related interrupt request flag (EIF; bit 4 of INTC) will be set. When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be cleared to disable other interrupts. The internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (TF; bit 5 of INTC), caused by a timer overflow. When the interrupt is enabled, the stack is not full and the TF bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (TF) will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, Register Bit No. 0 1 2 INTC (0BH) 3 4 5 6 7 Label EMI EEI ETI 3/4 EIF TF 3/4 3/4 other interrupt acknowledge signals are held until the "RETI" instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the interrupt subroutine, "RET" or "RETI" may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. No. Interrupt Source Priority Vector a b External Interrupt Timer/event Counter Overflow 1 2 04H 08H
The timer/event counter interrupt request flag (TF), external interrupt request flag (EIF), enable timer/event counter interrupt bit (ETI), enable external interrupt bit (EEI) and enable master interrupt bit (EMI) constitute an interrupt control register (INTC) which is located at 0BH in the data memory. EMI, EEI, ETI are Function
Controls the master (global) interrupt (1= enabled; 0= disabled) Controls the external interrupt (1= enabled; 0= disabled) Controls the timer/event counter 0 interrupt (1= enabled; 0= disabled) Unused bit, read as "0" External interrupt request flag (1= active; 0= inactive) Internal timer/event counter 0 request flag (1= active; 0= inactive) Unused bit, read as "0" Unused bit, read as "0" INTC register
Rev. 1.10
11
July 2, 2001
HT48R30A-1
used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (TF, EIF) are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction. It is recommended that a program does not use the "CALL subroutine" within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the "CALL" operates in the interrupt subroutine. Oscillator configuration There are 3 oscillator circuits in the microcontroller.
V
DD
and ignores an external signal to conserve power. If an RC oscillator is used, an external resistor between OSC1 and VDD is required and the resistance must range from 51kW to 1MW. The system clock, divided by 4, is available on OSC2, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of oscillation may vary with VDD, temperatures and the chip itself due to process variations. It is, therefore, not suitable for timing sensitive operations where an accurate oscillator frequency is desired. If the Crystal oscillator is used, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator. No other external components are required. In stead of a crystal, a resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required. If the internal RC oscillator is used, the OSC1 and OSC2 can be selected as gene ral I/O lines or an 32768Hz crystal oscillator (RTC OSC). Also, the frequencies of the internal RC oscillator can be 3.2MHz, 1.6MHz, 800kHz and 400kHz (depends on the options). The oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the power down mode, the system clock is stopped, but the oscillator still works within a period of 72ms. The WDT oscillator can be disabled by ROM code option to conserve power. Watchdog Timer - WDT The WDT clock source is implemented by a dedW D T P r e s c a le r
OSC1
470pF fS Y S /4 N M O S O p e n D r a in
OSC1
OSC2 C r y s ta l O s c illa to r ( In c lu d e 3 2 7 6 8 H z )
OSC2 RC O s c illa to r
System oscillator All of them are designed for system clocks, namely the external RC oscillator, the external Crystal oscillator and the internal RC oscillator, which are determined by ROM code option. No matter what oscillator type is selected, the signal provides the system clock. The HALT mode stops the system oscillator
S y s te m RTC C lo c k /4 OSC W DT OSC ROM Code O p tio n S e le c t 8 - b it C o u n te r
7 - b it C o u n te r
8 -to -1 M U X W D T T im e - o u t
W S0~W S2
Watchdog Timer
Rev. 1.10 12 July 2, 2001
HT48R30A-1
icated RC oscillator (WDT oscillator), RTC clock or instruction clock (system clock divided by 4), determines the ROM code option. This timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by ROM code option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation. The RTC clock is enabled only in the internal RC+RTC mode. Once the internal WDT oscillator (RC oscillator with a period of 72ms/5V normally) is selected, it is first divided by 256 (8-stage) to get the nominal time-out period of 18.6ms/5V. This time-out period may vary with temperatures, VDD and process variations. By invoking the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the WDTS) can give different time-out periods. If WS2, WS1, and WS0 are all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.4s/5V seconds. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operates in the same manner except that in the HALT state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external logic. The high nibble and bit 3 of the WDTS are reserved for user's defined flags, which can be used to indicate some specified status. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) or 32kHz crystal oscillator (RTC OSC) is strongly recommended, since the HALT will stop the system clock. WS2 0 0 0 0 1 1 1 1 WS1 0 0 1 1 0 0 1 1 WS0 0 1 0 1 0 1 0 1 Division Ratio 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 WDTS register The WDT overflow under normal operation will initialize "chip reset" and set the status bit "TO". But in the HALT mode, the overflow will initialize a warm reset and only the PC and SP are reset to zero. To clear the contents of WDT (including the WDT prescaler), three methods are adopted; external reset (a low level to RES), software instruction and a "HALT" instruction. The software instruction include "CLR WDT" and the other set - "CLR WDT1" and "CLR WDT2". Of these two types of instruction, only one can be active depending on the ROM code option - "CLR WDT times selection option". If the "CLR WDT" is selected (i.e. CLRWDT times equal one), any execution of the "CLR WDT" instruction will clear the WDT. In the case that "CLR WDT1" and "CLR WDT2" are chosen (i.e. CLRWDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip as a result of time-out. Power down operation - HALT The HALT mode is initialized by the "HALT" instruction and results in the following...
* The system oscillator will be turned off but
* *
* *
the WDT oscillator remains running (if the WDT oscillator is selected). The contents of the on chip RAM and registers remain unchanged. WDT and WDT prescaler will be cleared and recounted again (if the WDT clock is from the WDT oscillator). All of the I/O ports maintain their original status. The PD flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a "warm reset". After the TO and PD flags are examined, the reason for chip reset can be determined. The PD flag is cleared by system power-up or executing the "CLR WDT" instruction and is set when executing the "HALT" instruction. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the PC and
13 July 2, 2001
Rev. 1.10
HT48R30A-1
SP; the others remain in their original status. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by ROM code option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it awakens from an interrupt, two sequence may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to "1" before entering the HALT mode, the wake-up function of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 (system clock period) to resume normal operation. In other words, a dummy period will be inserted after a wake-up. If the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. The RTC oscillator still runs in the HALT mode (if the RTC oscillator is enabled). Reset There are three ways in which a reset can occur:
* RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation
RES
TO PD 0 u 0 1 1 0 u 1 u 1
RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT
Note: "u" stands for "unchanged" To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES reset) or the system awakes from the HALT state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up
VDD RES S S T T im e - o u t C h ip R eset tS
ST
Reset timing chart
V
DD
The time-out during HALT is different from other chip reset conditions, since it can perform a "warm reset" that resets only the PC and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to the initial condition when the reset conditions are met. By examining the PD and TO flags, the program can distinguish between different "chip resets".
Reset circuit from HALT will enable the SST delay.
Rev. 1.10
14
July 2, 2001
HT48R30A-1
HALT W DT
RES W a rm R eset
The functional unit chip reset status are shown below. PC Interrupt 000H Disable Clear Clear. After master reset, WDT begins counting Off Input mode Points to the top of the stack
OSC1
SST 1 0 - b it R ip p le C o u n te r S y s te m R eset
C o ld R eset
Prescaler WDT Timer/event Counter Input/output Ports SP
Reset configuration
Rev. 1.10
15
July 2, 2001
HT48R30A-1
The states of the registers is summarized in the table. Register TMR TMRC Program Counter MP ACC TBLP TBLH STATUS INTC WDTS PA PAC PB PBC PC PCC PG PGC Reset (Power On) xxxx xxxx 00-0 1000 000H -xxx xxxx xxxx xxxx xxxx xxxx --xx xxxx --00 xxxx --00 -000 0000 0111 1111 1111 1111 1111 1111 1111 1111 1111 --11 1111 --11 1111 ---- -111 ---- -111 WDT Time-out (Normal Operation) uuuu uuuu 00-0 1000 000H -uuu uuuu uuuu uuuu uuuu uuuu --uu uuuu --1u uuuu --00 -000 0000 0111 1111 1111 1111 1111 1111 1111 1111 1111 --11 1111 --11 1111 ---- -111 ---- -111 RES Reset (Normal Operation) uuuu uuuu 00-0 1000 000H -uuu uuuu uuuu uuuu uuuu uuuu --uu uuuu --uu uuuu --00 -000 0000 0111 1111 1111 1111 1111 1111 1111 1111 1111 --11 1111 --11 1111 ---- -111 ---- -111 RES Reset (HALT) uuuu uuuu 00-0 1000 000H -uuu uuuu uuuu uuuu uuuu uuuu --uu uuuu --01 uuuu --00 -000 0000 0111 1111 1111 1111 1111 1111 1111 1111 1111 --11 1111 --11 1111 ---- -111 ---- -111 WDT Time-out (HALT)* uuuu uuuu uu-u uuuu 000H -uuu uuuu uuuu uuuu uuuu uuuu --uu uuuu --11 uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu --uu uuuu ---- -uuu ---- -uuu
Note: "*" stands for "warm reset" "u" stands for "unchanged" "x" stands for "unknown"
Rev. 1.10
16
July 2, 2001
HT48R30A-1
Timer/Event Counter Timer/event counters (TMR) is implemented in the microcontroller. The timer/event counter contains an 8-bit programmable count-up counter and the clock may come from an external source or from the system clock or RTC. Using the internal clock sources, there are 2 reference time-bases for timer/event counter. The internal clock source can be selected as coming from fSYS (can always be optioned) or fRTC (enabled only system oscillator in the Int. RC+RTC mode) by ROM code option. The external clock input allows the user to count external events, measure time intervals or pulse widths, or to generate an accurate time base and PFD signals.
Label (TMRC)
Bits
Function To define the prescaler stages, PSC2, PSC1, PSC0= 000: fINT=fSYS/2 or fRTC/2 001: fINT=fSYS/4 or fRTC/4 010: fINT=fSYS/8 or fRTC/8 011: fINT=fSYS/16 or fRTC/16 100: fINT=fSYS/32 or fRTC/32 101: fINT=fSYS/64 or fRTC/64 110: fINT=fSYS/128 or fRTC/128 111: fINT=fSYS/256 or fRTC/256 To define the TMR0 active edge of timer/event counter 0 (0=active on low to high; 1=active on high to low) To enable/disable timer 0 counting (0=disabled; 1=enabled) Unused bit, read as"0" To define the operating mode 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMRC register
PSC0~PSC2
0~2
TE TON 3/4 TM0 TM1
3 4 5 6 7
fS fR
YS TC
M U
(1 /2 ~ 1 /2 5 6 ) X 8 - s ta g e P r e s c a le r 8 -1 M U X f IN
T
D a ta B u s TM 1 TM 0 TE T im e r /E v e n t C o u n te r P r e lo a d R e g is te r R e lo a d
ROM
C o d e O p tio n PSC2~PSC0 TM R
TM 1 TM 0 TON
P u ls e W id th M e a s u re m e n t M o d e C o n tro l
T im e r /E v e n t C o u n te r 1 /2
O v e r flo w to In te rru p t BZ BZ
Timer/Event Counter
Rev. 1.10 17 July 2, 2001
HT48R30A-1
There are 2 registers related to the timer/event counter; TMR ([0DH]), TMRC ([0EH]). Two physical registers are mapped to TMR location; writing TMR makes the starting value be placed in the timer/event counter preload register and reading TMR gets the contents of the timer/event counter. The TMRC is a timer/event counter control register, which defines some options. The TM0, TM1 bits define the operating mode. The event count mode is used to count external events, which means the clock source comes from an external (TMR) pin. The timer mode functions as a normal timer with the clock source coming from the fINT clock or RTC clock. The pulse width measurement mode can be used to count the high or low level duration of the external signal. The counting is based on the fINT clock or RTC clock. In the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to FFH. Once overflow occurs, the counter is reloaded from the timer/event counter preload register and generates the interrupt request flag (TF; bit 5 of INTC) at the same time. In the pulse width measurement mode with the TON and TE bits equal to one, once the ow to high (or high to low if the TE bits is "0") it will start counting until the TMR returns to the original level and resets the TON. The measured result will remain in the timer/event counter even if the activated transient occurs again. In other words, only one cycle measurement can be done. Until setting the TON, the cycle measurement will function again as long as it receives further transient pulse. Note that, in this operating mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues the interrupt request just like the other two modes. To enable the counting operation, the timer ON bit (TON; bit 4 of TMRC) should be set to 1. In the pulse width measurement mode, the TON will be cleared automatically after the measurement cycle is completed. But in the other two modes the TON can only be
Rev. 1.10 18
reset by instructions. The overflow of the timer/event counter 0/1 is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ETI can disable the corresponding interrupt services. In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register will also reload that data to the timer/event counter. But if the timer/event counter is turned on, data written to it will only be kept in the timer/event counter preload register. The timer/event counter will still operate until overflow occurs (a timer/event counter reloading will occur at the same time). When the timer/event counter (reading TMR) is read, the clock will be blocked to avoid errors. As clock blocking may results in a counting error, this must be taken into consideration by the programmer. The bit0~bit2 of the TMRC can be used to define the pre-scaling stages of the internal clock sources of timer/event counter. The definitions are as shown. The overflow signal of timer/event counter can be used to generate PFD signals for buzzer driving. Input/output ports There are 25 bidirectional input/output lines in the microcontroller, labeled from PA to PC and PG, which are mapped to the data memory of [12H], [14H], [16H] and [1EH] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction "MOV A,[m]" (m=12H, 14H, 16H or 1EH). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PCC, PGC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically (i.e. on-the-fly) under software control. To function as an input, the corresponding latch of the control register must write "1". The input source also depends on the control register. If the control register bit is "1",
July 2, 2001
HT48R30A-1
the input will read the pad state. If the control register bit is "0", the contents of the latches will move to the internal bus. The latter is possible in the "read-modify-write" instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H, 17H and 1FH. After a chip reset, these input/output lines remain at high levels or floating state (depending on the pull-high options). Each bit of these input/output latches can be set or cleared by "SET [m].i" and "CLR [m].i" (m=12H, 14H, 16H or 1EH) instructions. Some instructions first input data and then follow the output operations. For example, "SET [m].i", "CLR [m].i", "CPL [m]", "CPLA [m]" read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of wakPB0 I/O PB1 I/O PB0 Mode PB1 Mode PB0 Data PB1 Data PB0 Pad Status PB1 Pad Status I I x x x x I I I O x C x D I D O I C x D x D I O I B x 0 x 0 I ing-up the device. The highest 5-bit of port G are not physically implemented; on reading them a "0" is returned whereas writing then results in no-operation. See Application note. There is a pull-high option available for all I/O lines (bit option). Once the pull-high option of an I/O line is selected, the I/O line have pull-high resistor. Otherwise, the pull-high resistor is absent. It should be noted that a non-pull-high I/O line operating in input mode will cause a floating state. The PB0 and PB1 are pin-shared with BZ and BZ signal, respectively. If the BZ/BZ option is selected, the output signal in output mode of PB0/PB1 will be the PFD signal generated by timer/event counter 0 overflow signal. The input mode always remain in its original functions. Once the BZ/BZ option is selected, the buzzer output signals are controlled by the PB0 data register only. The I/O functions of PB0/PB1 are shown below. O I B x 1 x B I O O C C D0 D1 D0 D1 O O B C 0 D 0 D O O B C 1 D B D O O B B 0 x 0 0 O O B B 1 x B B
Note: I input, O output, D, D0, D1 data, B buzzer option, BZ or BZ, x don't care C CMOS output
Rev. 1.10
19
July 2, 2001
HT48R30A-1
P G 1 /P G 2 I/O C o n tr o l B it D a ta B u s D CK S Q PA0 PB0 PC0 PG0 ~PA ~PB ~PC ~PG 7 5 2 7 W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r Q m o d e o n ly PU V
DD
D a ta B it Q D CK S Q M U X M U X
W r ite D a ta R e g is te r
( P B 0 , P B 1 O n ly )
PB0 EXT
EXTEN ( P B 0 , P B 1 O n ly )
R e a d D a ta R e g is te r S y s te m W a k e -u p ( P A o n ly ) IN T fo r P G 0 O n ly
O P0~O P7
E X T = B Z fo r P B 0 o n ly , E X T = B Z fo r P B 1 o n ly , c o n tr o l= P B 0 d a ta r e g is te r
Input/output ports The PG0 is pin-shared with INT. In case of Internal RC+I/O system oscillator, the PG1 and PG2 are pin-shared with OSC1 and OSC2 pins. Once the Internal RC+I/O mode is selected, the PG1 and PG2 can be used as general purpose I/O lines. Otherwise, the pull-high resistors and I/O functions of PG1 and PG2 will be disabled. It is recommended that unused or not bonded out I/O lines should be set as output pins by software instruction to avoid consuming power under input floating state. Low voltage reset - LVR The microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~VLVR, such as changing a battery, the LVR will automatically reset the device internally. The LVR includes the following specifications:
* The low voltage (0.9V~VLVR) has to remain in
voltage state does not exceed 1ms, the LVR will ignore it and do not perform a reset function. * The LVR uses the OR function with the external RES signal to perform chip reset. The relationship between VDD and VLVR is shown below.
VDD 5 .5 V V
OPR
5 .5 V
V 3 .3 V 3 .0 V
LVR
0 .9 V
Note: VOPR is the voltage range for proper chip operation at 4MHz system clock.
their original state to exceed 1ms. If the low
Rev. 1.10
20
July 2, 2001
HT48R30A-1
V 5 .5 V
DD
V
LVR
LVR
D e te c t V o lta g e
0 .9 V 0V R e s e t S ig n a l
R eset *1
N o r m a l O p e r a tio n *2
R eset
Low voltage reset Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: Since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms delay enters the reset mode. ROM code option The following table shows all kinds of ROM code option in the microcontroller. All of the ROM code options must be defined to ensure proper system functioning. Items 1 2 3 4 5 6 7 8 9 10 11 Option WDT clock source: WDTOSC/fTID/RTCOSC/disable CLRWDT instructions: 1 or 2 instructions Timer/event counter clock sources: fSYS or RTCOSC PA wake-up (By bit) PA CMOS/SCHMITT input PA, PB, PC, PG pull-high enable/disable (By port) BZ/BZ enable/disable LVR enable/disable System oscillator Ext. RC, Ext.crystal, Int.RC+RTC or Int.RC+PG1/PG2 Int.RC frequency selection 3.2MHz, 1.6MHz, 800kHz or 400kHz Lock: unlock/lock
Rev. 1.10
21
July 2, 2001
HT48R30A-1
Application Circuits
RC oscillator for multiple I/O applications Crystal or ceramic resonator for multiple I/O applications
V VDD 100kW 51kW ~ 1M W OSC1 0 .1 m F 0 .1 m F 470pF NMOS o p e n d r a in OSC2 RES VSS IN T /P G 0 P B 0 /B Z P B 1 /B Z P C 0 /T M R 0 .1 m F 0 .1 m F C2 OSC2 RES VSS IN T /P G 0 P B 0 /B Z P B 1 /B Z P C 0 /T M R PA0~PA7 PB2~PB7 PC 1~PC 5 100kW C1 OSC1
DD
V
DD
VDD
PA0~PA7 PB2~PB7 PC 1~PC 5
H T 4 8 R 3 0 A -1
H T 4 8 R 3 0 A -1
Note: C1=C2=300pF if fSYS<1MHz Otherwise, C1=C2=0 Internal RC oscillator for multiple I/O applications
V
DD
Internal RC oscillator with RTC for multiple I/O applications
V
DD
VDD 100kW O S C 1 /P G 1 0 .1 m F O S C 2 /P G 2 0 .1 m F RES VSS IN T /P G 0
PA0~PA7 PB2~PB7 PC 1~PC 5 100kW
VDD
PA0~PA7 PB2~PB7 PC 1~PC 5
OSC1 0 .1 m F P B 0 /B Z P B 1 /B Z P C 0 /T M R 0 .1 m F 32768H z
OSC2 RES VSS IN T /P G 0
P B 0 /B Z P B 1 /B Z P C 0 /T M R
H T 4 8 R 3 0 A -1
H T 4 8 R 3 0 A -1
Note: The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high.
Rev. 1.10 22 July 2, 2001
HT48R30A-1
Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to register with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1 1(1) 1 1 1(1)
1 1(1)
Description
Instruction Cycle
Flag Affected Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C
1(1)
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] INCA [m] INC [m] DECA [m] DEC [m] 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 1 1(1) 1 1(1) Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement
Rev. 1.10
23
July 2, 2001
HT48R30A-1
Mnemonic Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result ACC Skip if decrement data memory is zero with result ACC Subroutine call Return from subroutine Return from subroutine and load immediate data ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC Clear bit of data memory Set bit of data memory 1 1(1) 1 1(1) 1(1) None None None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Description Instruction Cycle Flag Affected
Bit Operation
to
in in
to
Rev. 1.10
24
July 2, 2001
HT48R30A-1
Mnemonic Table Read TABRDC [m] Read ROM code (current page) to data memory and TBLH TABRDL [m] Read ROM code (last page) to data memory and TBLH Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PD TO(4),PD(4) TO(4),PD(4) None None TO,PD 2(1) 2(1) None None Description Instruction Cycle Flag Affected
Note: x: 8 bits immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected
(1) (2)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO is set and the PD is cleared. Otherwise the TO and PD flags remain unchanged.
(3) (1) (4)
Rev. 1.10
25
July 2, 2001
HT48R30A-1
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TC2 3/4 ADCM A,[m] Description Operation Affected flag(s) TC2 3/4 ADD A,[m] Description Operation Affected flag(s) TC2 3/4 ADD A,x Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
Rev. 1.10
26
July 2, 2001
HT48R30A-1
ADDM A,[m] Description Operation Affected flag(s) TC2 3/4 AND A,[m] Description Operation Affected flag(s) TC2 3/4 AND A,x Description Operation Affected flag(s) TC2 3/4 ANDM A,[m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC "AND" [m]
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC "AND" x
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC "AND" [m]
Rev. 1.10
27
July 2, 2001
HT48R30A-1
CALL addr Description Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack PC+1 PC addr TC2 3/4 CLR [m] Description Operation Affected flag(s) TC2 3/4 CLR [m].i Description Operation Affected flag(s) TC2 3/4 CLR WDT Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 0 PD 0 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H
Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0
Clear Watchdog Timer The WDT and the WDT Prescaler are cleared (re-counting from 0). The power down bit (PD) and time-out bit (TO) are cleared. WDT and WDT Prescaler 00H PD and TO 0
Rev. 1.10
28
July 2, 2001
HT48R30A-1
CLR WDT1 Description Preclear Watchdog Timer The TO, PD flags, WDT and the WDT Prescaler has cleared (re-counting from 0), if the other preclear WDT instruction has been executed. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PD flags remain unchanged. WDT and WDT Prescaler 00H* PD and TO 0* TC2 3/4 CLR WDT2 Description TC1 3/4 TO 0* PD 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
Preclear Watchdog Timer The TO, PD flags, WDT and the WDT Prescaler are cleared (re-counting from 0), if the other preclear WDT instruction has been executed. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PD flags remain unchanged. WDT and WDT Prescaler 00H* PD and TO 0* TC2 3/4 TC1 3/4 TO 0* PD 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
CPL [m] Description Operation Affected flag(s)
Complement data memory Each bit of the specified data memory is logically complemented (1's complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m] TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Rev. 1.10
29
July 2, 2001
HT48R30A-1
CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1's complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m] TC2 3/4 DAA [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0) (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
DEC [m] Description Operation Affected flag(s)
Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Rev. 1.10
30
July 2, 2001
HT48R30A-1
DECA [m] Description Operation Affected flag(s) TC2 3/4 HALT Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1
Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PD) is set and the WDT time-out bit (TO) is cleared. PC PC+1 PD 1 TO 0 TC2 3/4 TC1 3/4 TO 0 PD 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
INC [m] Description Operation Affected flag(s)
Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
INCA [m] Description Operation Affected flag(s)
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Rev. 1.10
31
July 2, 2001
HT48R30A-1
JMP addr Description Operation Affected flag(s) TC2 3/4 MOV A,[m] Description Operation Affected flag(s) TC2 3/4 MOV A,x Description Operation Affected flag(s) TC2 3/4 MOV [m],A Description Operation Affected flag(s) TC2 3/4 NOP Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump Bits of the program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. PC addr
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
No operation No operation is performed. Execution continues with the next instruction. PC PC+1
Rev. 1.10
32
July 2, 2001
HT48R30A-1
OR A,[m] Description Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC "OR" [m] TC2 3/4 OR A,x Description Operation Affected flag(s) TC2 3/4 ORM A,[m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC "OR" x
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC "OR" [m] TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
RET Description Operation Affected flag(s)
Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. PC Stack TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Rev. 1.10
33
July 2, 2001
HT48R30A-1
RET A,x Description Operation Affected flag(s) TC2 3/4 RETI Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. PC Stack ACC x
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit (bit 0; register INTC). PC Stack EMI 1 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
RL [m] Description Operation Affected flag(s)
Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
RLA [m] Description
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
Rev. 1.10
34
July 2, 2001
HT48R30A-1
RLC [m] Description Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7 TC2 3/4 RLCA [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
RR [m] Description Operation Affected flag(s)
Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Rev. 1.10
35
July 2, 2001
HT48R30A-1
RRA [m] Description Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0 TC2 3/4 RRC [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
RRCA [m] Description
Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
Rev. 1.10
36
July 2, 2001
HT48R30A-1
SBC A,[m] Description Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C TC2 3/4 SBCM A,[m] Description TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O
Operation Affected flag(s)
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O
Operation Affected flag(s)
SDZ [m] Description
Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
Rev. 1.10
37
July 2, 2001
HT48R30A-1
SDZA [m] Description Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1) TC2 3/4 SET [m] Description Operation Affected flag(s) TC2 3/4 SET [m].i Description Operation Affected flag(s) TC2 3/4 SIZ [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
Set data memory Each bit of the specified data memory is set to 1. [m] FFH
Set bit of data memory Bit "i" of the specified data memory is set to 1. [m].i 1
Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
Rev. 1.10
38
July 2, 2001
HT48R30A-1
SIZA [m] Description Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1) TC2 3/4 SNZ [m].i Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
Skip if bit "i" of the data memory is not 0 If bit "i" of the specified data memory is not 0, the next instruction is skipped. If bit "i" of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SUB A,[m] Description Operation Affected flag(s)
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O
SUBM A,[m] Description Operation Affected flag(s)
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O
Rev. 1.10
39
July 2, 2001
HT48R30A-1
SUB A,x Description Operation Affected flag(s) TC2 3/4 SWAP [m] Description Operation Affected flag(s) TC2 3/4 SWAPA [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SZ [m] Description
Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
Rev. 1.10
40
July 2, 2001
HT48R30A-1
SZA [m] Description Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0 TC2 3/4 SZ [m].i Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
Skip if bit "i" of the data memory is 0 If bit "i" of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
TABRDC [m] Description
Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
TABRDL [m] Description Operation Affected flag(s)
Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Rev. 1.10
41
July 2, 2001
HT48R30A-1
XOR A,[m] Description Operation Affected flag(s) TC2 3/4 XORM A,[m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC "XOR" [m]
Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC "XOR" [m] TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
XOR A,x Description
Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC "XOR" x TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
Rev. 1.10
42
July 2, 2001
HT48R30A-1
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Taipei Office) 11F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Holtek Semiconductor (Shanghai) Ltd. 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China Tel: 021-6485-5560 Fax: 021-6485-0313 Holmate Technology Corp. 48531 Warm Springs Boulevard, Suite 413, Fremont, CA 94539 Tel: 510-252-9880 Fax: 510-252-9885 Copyright O 2001 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.10
43
July 2, 2001

▲Up To Search▲

Price & Availability of HT48R30A

	To Download HT48R30A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .